Theses and Dissertations Collection

This dissertation presents a complete design flow for realizing our proposed silicon- based photonics circuits, which are able to generate multi-level optical signal outputs. The design flow only depends on the tools that are accessible to traditional integrated circuits designers and gets rid of the need to produce specific design tools for photonic circuit de- sign. The proposed photonics circuits use the heterogenerous integration method where the optical circuits are fabricated using IMEC-ePIXfab SiPhotonics ISIPP50G technology and the electrical circuits are simulated using the PDK of TSMC 65nm technology.

Compact Verilog-AMS modelings for optical blocks are developed, which include the models for continuous-wave lasers, couplers, photodiodes, electro-absorption modulators and waveguides/phase-shifters. All of the parameters used in the models above are derived from either the testing results of the standard microring modulator or the corresponding optical devices provided by IMEC ISIPP50G technology.

A coupling-based microring modulator, which is based on IMEC ISIPP50G technology, has been proposed and its design is realized using Verilog-A model in Cadence Virtuoso. The final simulation results show that the proposed coupling-based microring modulator is able to realize extinction ratio as large as 46dB when both the coupling coefficient tuning and resonant wavelength shifting are both enabled.

A photonic chip with the block size of 2500μm and 2500μm is fabricated using IMEC ISIPP50G technology and a PCB board for testing has been designed. Testing plan has been proposed and prospective testing results have been discussed.

A three-segment microring modulator—a proposed electro-optical modulator—has been proposed and is implemented in a scheme where equispaced optical PAM-4 output can be generated. The proposed scheme includes both coarse and precise tuning, which can be further categorized into lower “1” tuning and higher “0” tuning. A transmitter structure emanated from the proposed scheme is realized using TSMC 65nm LP technology and its simulation results derived from the extracted layout show 25-Gb/s optical PAM-4 output with the extinction ratio of 9dB and the PAM-4 energy efficiency of 0.5pJ/bit. The adapt- ability of the scheme can be justified by the following two results: a high percentage of level separation mismatch ratio (RLM ) can be achieved when ±10% phase-shifter length variation inside the three-segment microring is present; a total number of 4800 possible PAM-4 levels can be achieved.