Theses and Dissertations Collection

Comparators are one of the main building blocks in ADCs and there are quite a few

techniques for designing high-quality Comparators. Nevertheless, when two inputs

of a comparator are very close to each other, perfect device-matching is required to

reduce offset. Noise can also cause meta-stability and degrades the precision, and it

takes a very long time for the comparator to settle down, which adversely impacts

the conversion time and throughput of the ADCs. Furthermore, designing a large

number of high quality comparators is not affordable, which explains why highresolution Flash ADCs are not common. To address the aforementioned problem, in this work a new comparator design is proposed, named as the Soft Comparator. In the proposed Soft Comparator, the settling time is exploited to generate multiple bits instead of only one bit. This allows reducing the number of comparators in designing high resolution Flash ADCs by a big factor. It is capable of alleviating meta-stability and offset problems by relying on adjacent comparators that overlap with each other. Ultimately, it can speed up the data conversion time as the longest settling time will not be relevant anymore.