Theses and Dissertations Collection

Antennas and corresponding matching circuits for 5G and next-generation communications face many challenges, such as the port isolation between the transmit and receive chains of in-band full-duplex systems, and/or the theoretical bandwidth limitation for electrically small antennas, especially in the HF/VHF bands. Chapter 1 of this thesis discusses these challenges.

This thesis presents a characteristic-mode-based simultaneous transmit and receive (STAR) antenna design for in-band full-duplex (IBFD) systems in Chapter 2. The proposed method utilizes two characteristic modes of a conducting object as transmit and receive modes to achieve high isolation without a complicated self-interference cancellation circuit. The design example in this work is fully-planar, and it has a physical height of 1.6 mm. The measured -10 dB overlapped percentage S11 and S22 bandwidth of this STAR antenna is 2.5% and the measured isolation between the transmit and receive ports is greater than 30 dB over the entire frequency band of operation.

The bandwidth limitation of an electrically-small antenna can be overcome by employing active non-Foster matching circuits. Considering the time of designing stable non-Foster circuits, this dissertation presents a real-time machine-learning-assisted RF circuits synthesis toolbox. In Chapter 3, an application programming interface (API) and a toolbox were developed for automatically generating a massive amount of data samples for machine learning model training. The details of the automatic non-Foster circuits synthesis tool using different machine learning models are introduced in Chapter 4, including the artificial neural network (ANN), k-nearest neighbor (k-NN), and Gaussian process (GP) algorithms. A non-Foster circuit prototype was fabricated and measured to validate the proposed tool. The measured reactance shows a negative reactance-to-frequency slope, which confirms it is a non-Foster circuit. The proposed framework can be expanded to include more design features and other circuit topologies.